Semiconductor integrated circuits wafers are produced by a plurality of processes in a wafer fabrication facility (fab). These processes, and associated fabrication tools, may include thermal oxidation, diffusion, ion implantation, rapid thermal processing (RTP), chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxy, etch, and photolithography. In the production of an integrated semiconductor with 15 micron product, the semiconductor wafer may pass through up to 600 process steps.
Integrated circuits are typically fabricated by processing one or more wafers as a “lot” with a series of wafer fabrication tools (i.e., “processing tools”). Wafer lot identities (ID) are provided to monitor and control the wafer lots among various fabrication tools and automated systems via a manufacturing execution system (MES) or a management information system (MIS). Several wafers can be identified by a common lot identifier (the lot ID) and wafers in the same lot may be given individual identifiers (the wafer ID). A wafer carries an identifying mark that typically is made up of the lot ID and a wafer ID. The identifier is commonly generated by a computer program. A typical wafer identifying mark has 11 characters and is about 13 millimeters in length.
A client may use the wafer lot IDs to query processing status, projected finish date, engineering data or directly execute limited process control, such as holding a wafer lot or banking a wafer lot. The wafer lot ID is composed of multiple characters and may be encoded with reference to a manufacturing fab, lot created date or sequence number.
In contemporary semiconductor manufacturing systems, each of a plurality of die, or ICs, may be assigned an individual die ID to facilitate tracking of individual die to processing steps of the die. The die ID may correlate a particular die with a particular wafer, and thus a lot, from which the die was produced. For example, the die ID may comprise a wafer ID and a die ID assigned to the particular die. Moreover, the die ID may provide additional information related to the manufacture of the die. For example, the die ID may provide information that specifies a position of a wafer from which the die was produced, e.g., an x and y coordinate of the wafer.
During the fabrication stages, products (e.g., semiconductor wafers) are monitored and controlled for quality and yield using metrology tools. Wafers and die thereof may be subjected to chip probe (CP) tests, function tests, or other evaluation mechanisms. While such evaluation mechanisms are often successful in identifying manufacturing anomalies or errors, many product quality deficiencies may not be realized or observed until the ICs are deployed in a product. For example, many product reliability problems may not be realized until the ICs have been in use for some duration.
Fab clients and third party packaging and test companies may correlate die IDs with wafer IDs and may ascertain semiconductor manufacturing quality evaluations from a commonality analysis thereof. Particularly, location information that may be ascertained from a die ID may allow for a wafer product quality evaluation to be made by a third party via evaluation of a plurality of die and mapping the evaluation data to die locations of a wafer map. An engineering analysis may then be performed on the accumulated die data. In many instances, it is undesirable for entities external to a semiconductor fab to correlate a die with a wafer for the purposes of performing a commonality analysis or other product evaluation.